Parallel Bidirectional Port for a Soft-core Microprocessor Designing a System
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Abstract
This paper introduces a technique to design an bits bidirectional port to be connected with soft core microblaze processor system that is configurable on Spartan 3E slice. A soft core processor system with peripheral is designed using embedded design technique with integrated software environment (ISE tool) supplied by Xilinx. An interrupt system controller is added to the designed system to control the incoming interrupt signal to promote the interrupt service routine to deal with incoming data. The system performance is tested by sending and transmitting packets of data from and to a MatLab program using the P.C parallel port.
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THIS IS AN OPEN ACCESS ARTICLE UNDER THE CC BY LICENSE http://creativecommons.org/licenses/by/4.0/
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References
Scott Hauck and Andre DeHon, “Reconfigurable Computing The theory and practice Of FPGA- Based Computation”, Elsevier Inc.., 2008.
Xilinx Company, “Spartan-3E FPGA Starter Kit Board User Guide”, User Guide UG230 (v1.1), January-20-2011. http://www.xilinx.com/support/doc umentation/boards_and_kits/ug230. pdf.
Xilinx Company , ” Processor Local Bus (PLB) v4.6 (v1.02a)” data sheet DS531 December 20, 2007
Xilinx Company, “Multi-Port Memory Controller (MPMC) (v6.00.a) “, data sheet DS643, April 19, 2010.
Xilinx Company, “Block RAM (BRAM) Block (v1.00a) “, data sheet DS444, March 12, 2007. http://www.xilinx.com/support/doc umentation/ip_documentation/bram _block.pdf.
Xilinx Company, ” LMB BRAM Interface Controller (v2.10b)”, data sheet DS452, March 2, 2010.http://www.xilinx.com/suppor t/documentation/ip_documentation/ lmb_bram_if_cntlr.pdf.
Xilinx Company, ” Local Memory Bus (LMB) (v1.00a) “, data sheet DS445 , April 24. 2009.http://www.xilinx.com/suppor t/documentation/ip_documentation/ lmb_v10.pdf.
Xilinx Company,” ChipScope Pro ICON (v. 1.00a, 1.01a, 1.02a)”, data sheet DS646 March 24, 2008.
Xilinx Company, “XPS UART Lite (v1.00a)”, data sheet DS571 January 14, 2008.
Xilinx Company, “General XPS Purpose Input/Output (v1.00a)”, data sheet DS569 January 14, 2008. http://www.xilinx.com/support/doc umentation/ip_documentation/GPI O_v10.pdf.