Investigation of the Power Grid Accuracy by CMOS Transistor Network using Matlab/ Simulink
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Abstract
The design and analysis of the power distribution and supply system on a chip is a complex issue. The ideal network consists of millions of transistors, which act as energy consumers. This large number makes them complex in terms of design and analysis. Building typical algorithms with logical gates and working automatically is the best way to solve the problem of power grid complexity. In this research, it was proposed to design a new model for consumers on the basis of effective resistance. passive elements were used only in this model and based on the actual resistance and capacity of the logical gates. Consumers and power grids can adopt computational physics methods and consider each group of consumers in each subnet as within total circuits. Emphasis is placed on the interaction between consumers for energy distribution network and energy supply. Using Matlab/ Simulink, accuracy of the system is verified to determine the technical issues related to the operation of the system for power networks.
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References
Kogel T, et al. A modular simulation framework for architectural exploration of on-chip interconnection networks. Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis: ACM; 2003. pp. 7-12. DOI: https://doi.org/10.1145/944646.944648
Hemani A, et al. Network on chip: An architecture for billion transistor era. Proceeding of the IEEE NorChip Conference. Jaipur, India; 2009. pp. 110-116.
Chen HH, Ling DD. Power supply noise analysis methodology for deep-submicron VLSI chip design. The 34th annual Design Automation Conference: ACM; 1997. pp. 638-643. DOI: https://doi.org/10.1145/266021.266307
Chowdhury R, Bo Ruahm T. Design of a microgrid system. International Journal of Innovative Research in Science, Engineering and Technology 2015; 4 (7): 5262-5269. DOI: https://doi.org/10.15680/IJIRSET.2015.0407030
Manna K, Singh S, Chattopadhyay S, Sengupta I. Preemptive test scheduling for network-on-chip using particle swarm optimization. VLSI Design and Test: Springer; 2013. pp. 74-82. DOI: https://doi.org/10.1007/978-3-642-42024-5_10
Chandrakasan AP, Bowhill WJ, Fox F. Design of high-performance microprocessor circuits. 3rd ed. ed. New York: Wiley-IEEE press; 2010.
Gonzalez R, Gordon BM, Horowitz MA. Supply and threshold voltage scaling for low power CMOS. IEEE Journal of Solid-State Circuits 1997; 32 (8): 1210-1216. DOI: https://doi.org/10.1109/4.604077
Lasseter RH. Micro-grids: IEEE power engineering society winter meeting, New York, NY, 2015; 8 (01): 305-308.
Consoli E, Giustolisi G, Palumbo G. An accurate ultra-compact I–V model for nanometer MOS transistors with applications on digital circuits. IEEE Transactions on Circuits and Systems I 2012; 59 (1): 159-169. DOI: https://doi.org/10.1109/TCSI.2011.2158704
Gharpurey R, Kinget P. Ultra wideband: circuits, transceivers and systems. Ultra Wideband: Springer; 2008. pp. 1-23. DOI: https://doi.org/10.1007/978-0-387-69278-4_1