Review of Nanosheet Transistors Technology

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Firas N. A. Hassan Agha firas_nadheer@uomosul.edu.iq
Yasir H. Naif firas_nadheer@uomosul.edu.iq
Mohammed N. Shakib firas_nadheer@uomosul.edu.iq


Abstract

Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nano-dimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

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Hassan Agha, F. N. A. ., Naif, Y. H. ., & Shakib, M. N. . (2021). Review of Nanosheet Transistors Technology. Tikrit Journal of Engineering Sciences, 28(1), 40–48. https://doi.org/10.25130/tjes.28.1.05
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References

Saehoon Joung and SoYoung Kim, “Design Optimization of Dual Material Gate Nano Sheet Field Effect Transistors “,Authorized licensed use limited to: Auckland University of Technology.

E. Pop, S. Sinha, K. E. Goodson, "Heat generation and transport in nanometer-scale transistors", Proc. IEEE, vol. 94, no. 8, pp. 1587-1601, 2006. DOI: https://doi.org/10.1109/JPROC.2006.879794

P. Ye, T. Ernst and M. V. Khare, "The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore's Law," in IEEE Spectrum, vol. 56, no. 8, pp. 30-35, Aug. 2019. DOI: https://doi.org/10.1109/MSPEC.2019.8784120

G. Chalia and R. S. Hegde, “Study of Self-Heating Effects in Silicon Nano-Sheet Transistors”, IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), PP. 1-2, 2018. DOI: https://doi.org/10.1109/EDSSC.2018.8487097

S. Bangsaruntip et al., "High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling," 2009 IEEE International Electron Devices Meeting (IEDM), pp. 1-4,2009. DOI: https://doi.org/10.1109/IEDM.2009.5424364

S. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, 2015, pp. 1-3.

D. Jang, D. Yakimets et al., "Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node", IEEE Trans. Electron Dev., vol. 64, no. 6, pp. 2707-13, 2017. DOI: https://doi.org/10.1109/TED.2017.2695455

N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," 2017 Symposium on VLSI Technology, Kyoto, 2017, pp. T230-T231.

M. Chen et al., "TMD FinFET with 4 nm thin body and back gate control for future low power technology," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2015, pp. 32.2.1-32.2.4.

M. Chen et al., "TMD FinFET with 4 nm thin body and back gate control for future low power technology," 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, 2015, pp. 32.2.1-32.2.4. DOI: https://doi.org/10.1109/IEDM.2015.7409813

IRDS Report, http://irds.ieee.org/reports, 2018.

N. Singh et al., “Ultra-narrow silicon nanowire gate-all-around cmos devices: Impact of diameter, channel-orientation and low temperature on device performance,” in 2006 International Electron Devices Meeting, Dec 2006, pp. 1–4. DOI: https://doi.org/10.1109/IEDM.2006.346840

Jingyun Zhang , Xin Miao, Robin Chao and Ali Razavieh “Channel Geometry Impact and Narrow Sheet Effect of Stacked Nanosheet” Conference Paper · December 2018.

Chandan Kumar Jha etal“Impact of LER on Mismatch in Nanosheet Transistors for 5nm-CMOS” 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2020, pp. 1-4.

H. -. Cho et al., "Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications," 2016 IEEE Symposium on VLSI Technology, Honolulu, HI, 2016, pp. 1-2. DOI: https://doi.org/10.1109/VLSIT.2016.7573359

N. Loubet et al., "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET," Symposium on VLSI Technology, Kyoto, 2017, pp. T230-T231.

Firas Natheer Abdul-kadir, Khalid khaleel Mohammad, Yasir Hashim “Investigation and design of ion-implanted MOSFET based on (18 nm) channel length”, Journal of TELKOMNIKA Telecommunication, Computing, Electronics and Control Vol. 18, No. 5, October 2020, pp. 2635-2641. DOI: https://doi.org/10.12928/telkomnika.v18i5.15958

Pragya Kushwaha et al“Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Aroun MOSFET”, IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE, SAN JOSE, CA, 2019. DOI: https://doi.org/10.1109/S3S46989.2019.9320660

Samuel Greengard,”Can Nanosheet Transistors Keep Moore’s Law Alive?”, Communications of the ACM, March 2020, Vol. 63 No. 3, Pages 10-12. DOI: https://doi.org/10.1145/3379493

Bae, Geumjong et al. “3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications.” 2018 IEEE International Electron Devices Meeting (IEDM) (2018): pp. 28.7.1-28.7.4.

Shubo Zhang, “Review of Modern Field Effect Transistor Technologies for Scaling”, J. Phys.: Conf. Ser., vol. 1617-012054, pp. 1-8, 2020. DOI: https://doi.org/10.1088/1742-6596/1617/1/012054

George V. Angelov ,1 Dimitar N. Nikolov,2 and Marin H. Hristov1 Technology and Modeling of Nonclassical Transistor Devices”, Journal of Electrical and Computer Engineering, Vol. 2019, Article ID 4792461, 18 pages, 2019. DOI: https://doi.org/10.1155/2019/4792461

Mayur Bhole, Aditya Kurude, Sagar Pawar, “3D Tri-Gate Transistor Technology and Next Generation FPGAs”, International Journal of Engineering Sciences & Research Technology, vol. 2, no. 10, pp. 2670-2675, 2013.

Noh, M-S.; et al. "Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows". Proc. SPIE. 7640: 76400S. doi:10.1117/12.848194, 2010. DOI: https://doi.org/10.1117/12.848194

Axelrad, V.; et al. "16nm with 193nm immersion lithography and double exposure". Proc. SPIE. 7641: 764109, doi:10.1117/12.846677, 2010. DOI: https://doi.org/10.1117/12.846677

S. P. Wong et al, “A Density Metric for Semiconductor Technology,” in Proceedings of the IEEE, vol. 108, no. 4, pp. 478-482, April 2020. DOI: https://doi.org/10.1109/JPROC.2020.2981715

R. Xie et al., "A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels," 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2016, pp. 2.7.1-2.7.4, 2016.

Firas Natheer Abdul-kadir, Yasir Hashim, Mohammed Nazmus Shakib, Faris Hassan Taha, "Electrical Characterization of Si Nanowire GAA-TFET Based on Dimensions Downscaling", International Journal of Electrical and Computer Engineering (IJECE), Vol. 11, No. 1, pp. 780-787, February 2021. DOI: https://doi.org/10.11591/ijece.v11i1.pp780-787

Nancy Cohen, “Samsung at foundry event talks about 3nm, MBCFET developments”, TechXplore, 2019, May 18, https://techxplore.com/news/2019-05-samsung-foundry-event-3nmmbcfet.html

Sung-Young Lee, Eun-Jung Yoon, "A novel sub-50 nm multi-bridge-channel MOSFET (MBCFET) with extremely high performance," Digest of Technical Papers. 2004 Symposium on VLSI Technology, Honolulu, HI, USA, 2004, pp. 200-201. DOI: https://doi.org/10.1109/VLSIT.2004.1345478

Debajit Bhattacharya and Niraj K. Jha “FinFETs: From Devices to Architectures” Advances in Electronics, Vol. 2014, Article ID 365689, 21 pages, 2014. DOI: https://doi.org/10.1155/2014/365689

J. Zhang et al., "Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications," 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2019, pp. 11.6.1-11.6.4. DOI: https://doi.org/10.1109/IEDM19573.2019.8993490

Firas Natheer Abdul-kadir Agha, Yasir Hashim, Mohammed Nazmus Shakib, “Temperature Impact on The ION/IOFF Ratio of Gate All Around Nanowire TFET”, 2020 IEEE International Conference on Semiconductor Electronics (ICSE), 2020, Malaysia.

Amita, A. Gorad and U. Ganguly, "Analytical Estimation of LER-Like Variability in GAA Nano-Sheet Transistors," 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Hsinchu, Taiwan, 2019, pp. 1-2. DOI: https://doi.org/10.1109/VLSI-TSA.2019.8804637

S. Joung and S. Kim, "Leakage Performance Improvement in Multi-Bridge-Channel Field Effect Transistor (MBCFET) by Adding Core Insulator Layer," 2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Udine, Italy, 2019, pp. 1-4. DOI: https://doi.org/10.1109/SISPAD.2019.8870498

Henry H. Radamson et al., " State of the Art and Future Perspectives in Advanced CMOS Technology," Nanomaterials, vol. 10, no. 8, p. 1555, 2020. DOI: https://doi.org/10.3390/nano10081555

Jianting Ye et al. “Transistors on Nano-sheets Beyond Graphene”, 2013 International Conference on Solid State Devices and Materials, Fukuoka, 2013, pp682-683.

G. Bae et al., "3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications," 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 28.7.1-28.7.4. DOI: https://doi.org/10.1109/IEDM.2018.8614629

W. C. Jeong et al., "True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break," 2018 IEEE Symposium on VLSI Technology, Honolulu, HI, 2018, pp. 59-60. DOI: https://doi.org/10.1109/VLSIT.2018.8510682

D. Ha et al., "Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications," 2017 Symposium on VLSI Technology, Kyoto, 2017, pp. T68-T69. DOI: https://doi.org/10.23919/VLSIT.2017.7998202

B. Parvais et al., "The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET," 2009 International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, 2009, pp. 80-81. DOI: https://doi.org/10.1109/VTSA.2009.5159300

S. Barraud et al., "Performance and design considerations for gate-all-around stacked-NanoWires FETs," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 29.2.1-29.2.4. DOI: https://doi.org/10.1109/IEDM.2017.8268473

K. Uchida, J. Koga, R. Ohba, T. Numata and S. I. Takagi, "Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI MOSFETs," International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), Washington, DC, USA, 2001, pp. 29.4.1-29.4.4.

X. He et al., "Impact of aggressive fin width scaling on FinFET device characteristics," 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2017, pp. 20.2.1-20.2.4. DOI: https://doi.org/10.1109/IEDM.2017.8268427

Amita, S. Mittal and U. Ganguly, "The First Compact Model to Determine VT Distribution for DG-FinFET Due to LER," in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4772-4779, Nov. 2018. DOI: https://doi.org/10.1109/TED.2018.2870282

S. Kim, M. Guillorn, I. Lauer, P. Oldiges, T. Hook and M. Na, "Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond," 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Rohnert Park, CA, 2015, pp. 1-3. DOI: https://doi.org/10.1109/S3S.2015.7333521

Sung-Young Lee et al., "A novel multibridge-channel MOSFET (MBCFET): fabrication technologies and characteristics," in IEEE Transactions on Nanotechnology, vol. 2, no. 4, pp. 253-257, Dec. 2003.. DOI: https://doi.org/10.1109/TNANO.2003.820777

E Mohapatra, TP Dash, J Jena, S Das, J Nanda, CK Maiti, “Performance Analysis of Si-Channel Nanosheet FETs with Strained SiGe Source/Drain Stressors” chapter in book Advances in Electrical Control and Signal Systems, Springer, 329-337, 2020. DOI: https://doi.org/10.1007/978-981-15-5262-5_23

Ali Razavieh et al. “Effective Drive Current in Scaled FinFET and NSFET CMOS Inverters”, 2018 76th Device Research Conference (DRC), 2018, pp. 1-2. DOI: https://doi.org/10.1109/DRC.2018.8442220

J. Yao et al., "Physical Insights on Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around NSFET for 5 nm Technology Node," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 841-848, 2018. DOI: https://doi.org/10.1109/JEDS.2018.2858225

D. Ryu, M. Kim, J. Yu, S. Kim, J. Lee and B. Park, "Investigation of Sidewall High-k Interfacial Layer Effect in Gate-All-Around Structure," in IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1859-1863, April 2020. DOI: https://doi.org/10.1109/TED.2020.2975255

C. K. Jha, K. Aditya, C. Gupta, A. Gupta and A. Dixit, "Single Event Transients in Sub-10nm SOI MuGFETs Due to Heavy-Ion Irradiation," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 395-403, June 2020.

P. Kumar, S. Yadav and P. K. Pal, "Analysis of Nanosheet Field Effect Transistor (NSFET) for device and circuit perspective," 2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE), Dehradun Uttarakhand, India, 2019, pp. 183-186. DOI: https://doi.org/10.1109/WITCONECE48374.2019.9092925

A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma and Y. S. Chauhan, "Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport," in IEEE Journal of the Electron Devices Society, doi: 10.1109/JEDS.2020.3019927. DOI: https://doi.org/10.1109/JEDS.2020.3019927

C. K. Jha, K. Aditya, C. Gupta, A. Gupta and A. Dixit, "Single Event Transients in Sub-10nm SOI MuGFETs Due to Heavy-Ion Irradiation," in IEEE Transactions on Device and Materials Reliability, vol. 20, no. 2, pp. 395-403, June 2020. DOI: https://doi.org/10.1109/TDMR.2020.2985029

Eleena Mohapatra et al. “Strain induced variability study in Gate-All-Around vertically-stacked horizontal nanosheet transistors”, Physica Scripta, pp. 1-13, 2020. DOI: https://doi.org/10.1088/1402-4896/ab89f5

Firas Natheer Abdul-kadir Agha, Yasir Hashim, Waheb Abduljabbar Shaif, “Temperature characteristics of Gate all around nanowire channel Si-TFET”, Journal of Physics: Conference Series, 2020. (Accepted) DOI: https://doi.org/10.1088/1742-6596/1755/1/012045