Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E
Article Sidebar
Main Article Content
Abstract
This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images. The architecture is designed in a way based on modules that a share between JPEG encoder and decoder circuit. Each module was designed to implement a forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they are described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, that given the full modular pipeline depth. The CODEC could process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.
Metrics
Article Details
This work is licensed under a Creative Commons Attribution 4.0 International License.
THIS IS AN OPEN ACCESS ARTICLE UNDER THE CC BY LICENSE http://creativecommons.org/licenses/by/4.0/
Plaudit
References
Achaya T, Tsai P. JPEG2000 Standard for Image Compression Awiley-Interscience; 2005. DOI: https://doi.org/10.1002/0471653748
Tiwari T, Reddy SC. Performance measurement of a fully pipelined JPEG codec on emulation platform. 2nd International Advance Computing Conference (IACC), IEEE 2010: p. 167–171. DOI: https://doi.org/10.1109/IADCC.2010.5423018
Yang H, Wang L. Joint optimization of run-length coding, huffman coding, and quantization table with complete baseline JPEG decoder compatibility. IEEE Transactions on Image Processing 2009; 18(1): 63–74. DOI: https://doi.org/10.1109/TIP.2008.2007609
Volcan L, Porto RC, Bampi S, Silva IS. A FPGA based design of a multiplierless and fully pipelined JPEG compressor. 8th Euromicro conference on Digital System Design (DSD’05) 2005; IEEE: p. 210–213.
Tumeo A, Monchiero M, Palermo G, Ferrandi F, Sciuto D. An internal partial dynamic reconfiguration implementation of the JPEG encoder for low-cost FPGAs. IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07) 2007; p. 449–450. DOI: https://doi.org/10.1109/ISVLSI.2007.25
Nishikawa Y, Kawahito S, Inoue T. A parallel image compression system for high-speed cameras. Imaging Systems and Techniques, IEEE International Workshop on 2007: p. 53–57.
Leong MP, Leong HW. A variable-radix digit-serial design methodology and its application to the discrete cosine transform. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2003; 11 (1): 90–104. DOI: https://doi.org/10.1109/TVLSI.2003.811099
Gloster C, Gay JW, Amoo M, Chouikha M. Optimizing the design of a configurable digital signal processor for accelerated execution of the 2-D discrete cosine transform. 39th Hawaii International Conference on System Sciences 2006: p. 250c-250c. DOI: https://doi.org/10.1109/HICSS.2006.374
Megalingam RK, Krishnan V, Sarma V, Mithun M, Srikumar R. Hardware implementation of low power, high speed DCT/IDCT based digital image watermarking. International Conference on Computer Technology and Development 2009: p. 535–539. DOI: https://doi.org/10.1109/ICCTD.2009.195
Sun CC, Donner P, Gotze J. Low-complexity multi-purpose ip core for quantized discrete cosine and integer transform. Circuits and Systems, ISCAS 2009. IEEE International Symposium: p. 3014–3017. DOI: https://doi.org/10.1109/ISCAS.2009.5118437
Agostini LV, Bampi S, Silva IS. High throughput architecture of JPEG compressor for color images targeting FPGAs. Electronics, Circuits and Systems, ICECS '06. 13th IEEE International Conference 2016: p.180–183.