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Tikrit Journal of Engineering Sciences (2005) 24(3) 15- 20

Design and Implementation of a Gray Scale JPEG CODEC on Spartan-3E

Abdulkreem Mohameed  Salih  Ahlam Fadhil Mahmood
Computer Engineering Department, University of Mosul, Iraq

This paper presents the design and implementation of the hardware JPEG CODEC for grayscale images. The architecture is designed in a way based on modules that a share between JPEG encoder and decoder circuit. Each module was designed to implement a forward and backward function and they have separate control signals. The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation. The designed architectures are detailed in this paper and they are described in VHDL, simulated and physically mapped to XC3S500 FPGAs. The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, that given the full modular pipeline depth. The CODEC could process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.


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Keywords: JPEG, CODEC, compressor, decompressor, FPGA, DCT.

How to cite

TJES: Salih AM, Ahlam FM. Design and implementation of a gray scale JPEG CODEC on spartan-3E. Tikrit Journal of Engineering Sciences 2017; 24 (3): 15-20.
APA: Salih A. M. & Ahlam F. M. (2017). Design and implementation of a gray scale JPEG CODEC on spartan-3E. Tikrit Journal Of Engineering Sciences, 24(3), 15-20.
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