vol23no2pa9

References

[1] Jihong, L., Baorui, L., and Deqin, L., “Design and Implementation of FPGA-Based Modified BKNN Classifier”, International Journal of Computer Science and Network Security (IJCSNS), Vol. 7, No. 3, pp. 67-71, March 2007.
[2] Shihab, K., “A Back Propagation Neural Network for Computer Network Security”, Journal of Computer Science, Vol. 2, No. 9, pp. 710-715, 2006.
[3] Rafid, A. Kh., “Hardware Implementation of Backpropagation Neural Networks on Field programmable Gate Array (FPGA)”, Al-Rafidain Engineering Journal, Vol. 16, No.3, pp. 62-70, Aug. 2008.
[4] Antony, W. S., Medhat, M., and Shawki, A., ”The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study”, IEEE Transactions On Neural Networks, Vol. 18, No. 1, pp. 240-252, January 2007.
[5] Chandra, B., and Paul, P. V., “Applications of Cascade Correlation Neural Networks for Cipher System Identification”, World Academy of Science, Engineering and Technology, Vol. 26, pp. 311-314, 2007.

Tikrit Journal of Engineering Sciences (2016) 23(2) 74- 85

Hardware Implementation of Artificial Neural Network for Data Ciphering

Sahar L. Kadoory Toka A. Fatehi Qutaiba A. Hasan
Electronics Engineering College, University of Mosul, Iraq Petroleum and Minerals Engineering College, Tikrit University, Iraq

Abstract

This paper introduces the design and realization of multiple blocks ciphering techniques on the FPGA (Field Programmable Gate Arrays). A back propagation neural networks have been built for substitution, permutation and XOR blocks ciphering using Neural Network Toolbox in MATLAB program. They are trained to encrypt the data, after obtaining the suitable weights, biases, activation function and layout. Afterward, they are described using VHDL and implemented using Xilinx Spartan-3E FPGA using two approaches: serial and parallel versions. The simulation results obtained with Xilinx ISE 9.2i software. The numerical precision is chosen carefully when implementing the Neural Network on FPGA. Obtained results from the hardware designs show accurate numeric values to cipher the data. As expected, the synthesis results indicate that the serial version requires less area resources than the parallel version. As, the data throughput in parallel version is higher than the serial version in rang between (1.13-1.5) times. Also, a slight difference can be observed in the maximum frequency.

Download Full-Text PDF

Keywords: Back propagation, Ciphering, Encryption, FPGA, Neural Network, VHDL.

How to cite

TJES: Kadoory SL, Fatehi TA, Hasan QA. Hardware Implementation of Artificial Neural Network for Data Ciphering. Tikrit Journal of Engineering Sciences 2016; 23 (2):74-85.
APA: Kadoory, S. L., Fatehi, T. A., & Hasan, Q. A. (2016). Hardware Implementation of Artificial Neural Network for Data Ciphering. Tikrit Journal of Engineering Sciences, 23(2), 74-85.