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References

[1] Hsu Kuan Chun Issac, ” A 70 MHz CMOS Band-pass Sigma-Delta Analog-to-Digital Converter for Wireless Receivers”, MSc Thesis, Dept. Electrical. Electronic Eng., Hong Kong Univ., China, pp.100, 1999.
[2] Eric T. King, Aria Eshraghi, Ian Galton, and Terri S. Fiez, “A Nyquist-Rate Delta–Sigma A/D Converter”, IEEE Journal of Solid-State Circuits, Vol. 33, No. 1, January, pp.45-52. 1998.
[3] Zheng Chen, “VLSI Implementation of a High-Speed Delta-Sigma Analog to Digital Converter”, MSc Thesis, Russ College of Engineering and Technology, Ohio University, USA, pp.127, 1997.
[4] Rajaram Mohan Roy Koppula, Sakkarapani Balagopal, Student Members, IEEE and Vishal Saxena “Efficient Design and Synthesis of Decimation Filters for Wideband Delta-Sigma ADCs”, IEEE, 26-28, pp. 380-385, Sept 2011.
[5] Cai Jun, Zheng Changlu and Xu Guanhuai, “A Fourth-Order 18-b Delta–Sigma A/D Converter”, High Density Microsystem Design and Packaging and Component Failure Analysis Conference, IEEE, 27-29, pp.1-4, June 2005.

Tikrit Journal of Engineering Sciences (2016) 23(2) 21- 28

Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA

Khalid Khaleel Mohammed Mohammed Idrees Dawod
College of Electronics Engineering, University of Mosul, Iraq

Abstract

A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 MHz. The proposed decimation filter design is consists of a second order Cascaded Integrator Comb filter (CIC) followed by two finite impulse response (FIR) filters. This architecture reduces the need for multiplication which is need very large area. This architecture implements a decimation ratio of 256 and allows a maximum resolution of 13 bits in the output of the filter. The decimation filter was designed and tested in Xilinx system generator tool which reduces the design cycle by directly generating efficient VHDL code. The results obtained show that the overall Sigma-Delta ADC is able to achieve an ENOB (Effective Number Of Bit) of 13.71 bits and SNR of 84.3 dB.

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Keywords:Sigma-Delta modulation, Decimation filter, A/D conversion, Oversampling, FPGA, VHDL.

How to cite

TJES: Mohammed KK, Dawod MI. Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA. Tikrit Journal of Engineering Sciences 2016;23(2):21-28.
APA: Mohammed, K. K., & Dawod, M. I. (2016). Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA. Tikrit Journal of Engineering Sciences, 23(2), 21-28.