[1] Mohamed. S. Haji Ali, Maan M. Shaker and Thair A. Salih, “Design and Implementation of a Dynamic Analog Matched Filter Using FPAA Technology”, World Academy of Science, Engineering and Technology, vol. 48, pp.206-210, 2008.

[2] Donald Hearn and M. Pauline Baker ,M.Pauline Baker, “Computer Graphics, C version” , 2nd edition. Prentice Hall, Inc. 1997.

[2] T. M. ShafiquI Khalid and M. Kaykobad,“an Efficient Line Algorithm”, Journal of Circuits and Systems, IEEE 39th Midwest symposium, Vol. 3, Pages: 1280- 1282 , 1996.

[3] Edward Angle and Don Morrison,”Speeding Up Bresenham’s Algorithim“, university of new mexico, November 1991 , IEEE Computer Graphics & Application.

Tikrit Journal of Engineering Sciences (2013) 20(2) 37-47

Hardware Implementation of 3D-Bresenham’s Algorithm Using FPGA

Basma Mohammed Kamal Younis Ne’am Salim Mohammed Sheet
Computer Technical Eng. Dept., Technical College, Mosul, Iraq


Traditional 3D-Bresenham’s algorithm is efficient in generating lines on raster systems using only integer calculations. This algorithm is needed as a solution of hidden surface problem using depth-buffer method to calculate z value for each pixel, while calculated values of x and y are used to address frame buffer memory, z value is used to test hidden surface by saving the closest depth in depth buffer. In this paper Bresenham’s algorithm for plotting 3D-lines is examined then modified to simplify hardware requirements during implementation phase. Basing on efficiency of the algorithm on the space symmetry an enhanced version of this algorithm is implemented using OpenGL. Experimental results confirm results calculated theoretically for both traditional and modified algorithms. The hardware implementation is accomplished for real time applications, and a graphic sub-system is designed using FPGA. Finally, a comparison is accomplished for Spartan3E utilization which is used to implement the hardware unit.

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KeywordsComputer Graphics, Bresenham, Pixel, Scan Conversion, FPGA.

How to cite

TJES: Younis BMK, Sheet NSM. Hardware Implementation of 3D-Bresenham’s Algorithm Using FPGATikrit Journal of Engineering Sciences 2013; 20(2): 37-47.
APA: Younis, B. M. K., & Sheet, N. S. M. (2013). Hardware Implementation of 3D-Bresenham’s Algorithm Using FPGA.. Tikrit Journal of Engineering Sciences, 20(2), 37-47.