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Tikrit Journal of Engineering Sciences (2011) 18(3) 89- 105
Hardware Implementation of Line Clipping A logarithm by using FPGA
Amar I. Dawod, Computer Engineering Dept., University of Mosul, Iraq
The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance, the clipping is still a bottleneck of any graphical system. Therefore, its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA). The designed hardware unit consists of two parts: the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the designed unit is capable of clipping (232524) line segments per second.
Keywords: Clipping, Graphical Pipeline, Real time, FPGA.
How to cite
TJES: Dawod AI. Hardware Implementation of Line Clipping A logarithm by using FPGA. Tikrit Journal of Engineering Sciences 2011; 18(3): 89-105
APA: Dawod A. I., (2011). Hardware Implementation of Line Clipping A logarithm by using FPGA. Tikrit Journal of Engineering Sciences, 18(3), 89-105.